In a radio communication system, it is generally required to perform modulation/demodulation for transmitted and received data. In other words, it is necessary at the transmitting side to perform, for data signals to be transmitted, modulation such as PSK (Phase Shift Keying, e.g., BPSK (Binary PSK), QPSK (Quadrature PSK) or 8PSK) or QAM (Quadrature Amplitude Modulation, e.g., 16QAM, 64QAM or 256QAM), spreading, and the like. On the other hand, it is necessary at the receiving side to perform, for received data signals, synchronous processing, demodulation, despreading, and the like.
These processes are intended mainly for radio symbol units (complex IQ signals), and thus it is required to execute a large number of complex arithmetic processes (complex multiplication, complex addition and the like). Further, upon the demodulation, the dynamic range of arithmetic-processing data broadens out beyond the necessity. Therefore, it is also necessary at the intermediate stage of processing to streamline the processing, for example, by normalizing the result of complex arithmetic operation for each piece of data and then performing the next arithmetic operation.
Conventionally, there has been adopted a technique to implement a dedicated hardware circuit for each process in order to be compatible with modulation/demodulation and synchronous processing in a single radio communication method at high speed and low power consumption. For example, PTL 1 discloses a dedicated circuit which calculates, upon RAKE synthesis, a normalization coefficient by using a plurality of channel estimate values.
Further, expectations have been recently raised for software radio technologies which can cope with a plurality of radio methods by one system. However, contents of modulation/demodulation/synchronous processing have the characteristic of basically differing from one to another between various radio communication methods which have been standardized, while being partially similar to each other.
Accordingly, in a case of using the conventional technique where the dedicated hardware circuit is implemented for each radio communication method in order to cope with modulation/demodulation/synchronous processing in a plurality of radio communication methods in a simple manner, it requires a plurality of dedicated hardware circuits corresponding to the number of adopted radio communication methods. Therefore, there is a problem that the space overhead of circuits is very high. Further, there is also a problem that the flexibility for modification or extension of processing is low.
There have been already proposed first and second related arts for addressing the above-mentioned problems. Hereinafter, these first and second related arts will be described one by one.
[First Related Art]
PTL 2 discloses a technique to make a dedicated hardware circuit compatible with a plurality of radio communication methods, by configuring the dedicated hardware circuit to be able to be set thereto various parameters with the emphasis on high-speed performance and power efficiency. Specifically, a dedicated processing engine, which forms a wireless communication device, is configured to be able to be reset in order that the dedicated processing engine may be compatible with a plurality of baseband processes, so that the dedicated processing engine is made flexibly compatible with a plurality of radio communication methods.
However, in this case, there is a problem that although it is relatively easy to address the change in a part of processing parameters in the arithmetic expression, it is difficult to be compatible with radio communication methods such as CDMA (Code Division Multiple Access) and OFDM (Orthogonal Frequency Division Multiplexing), whose fundamental processing algorithms of demodulation are different from each other.
Further, it is also difficult to be able to modify arithmetic processing data units, the repeat count of arithmetic processing, the detailed order of arithmetic operations, the order of processing between processing engines (dedicated hardware circuits), and the like. Configuring them so as to be able to be modified, there cause a problem of complicating the configuration of connections between dedicated hardware circuits, after all, which leads to an increase in the space overhead, and a problem that it is not possible to address the extension of specifications, which will be expected in the future like change in the order of processing within the processing engine.
Note that as similar techniques, PTLs 3 and 4 each disclose a technique to address system change by making a dedicated co-processor (hardware circuit) capable of being set thereto parameters and by controlling the dedicated co-processor under a processor for control.
However, as with the above-mentioned PTL 2, although it is possible to address changes in a part of processing parameters and the number of parallel processes, or the like, it is merely possible to address the change within a certain fixed range of processes. Therefore, there is a problem that it is difficult to be able to address modifications of the fundamental processing algorithm and the order of arithmetic operations, and the like.
[Second Related Art]
As another related art, PTL 5 discloses a technique to perform software processing by using a signal processing processor (DSP: Digital Signal Processor). Specifically, communication processing is executed by using a typical signal processing processor, a DMA (Direct Memory Access) controller for speeding up memory access and the like, thereby flexibly addressing various signal processes.
However, in modulation/demodulation/synchronous processing for radio communication, it is required to normalize data before and after special arithmetic processing such as complex arithmetic processing (in more detail, to calculate a normalization coefficient and to perform normalization using this coefficient). Therefore, the typical signal processing processor requires processing instructions (arithmetic cycles) more than those required by dedicated hardware which can execute these processes in a pipelined parallel manner, so that there is a problem that the number of processing cycles significantly increases.
Further, although the flexibility for processing modification is ensured, access latency from a processor to a memory leads to the performance overhead, for example. Therefore, after all, there is also a problem that it is difficult to speed up. Even when the DMA controller is used for the memory access, in the case of the software processing by the processor, separate cycles are required for a load/store instruction for the memory and an arithmetic processing instruction. Therefore, the software processing runs at lower speed than the dedicated hardware processing. On the other hand, it is required to raise a clock frequency in the case of increasing the speed, so that there is a problem that the power consumption increases.